K, Janshi Lakshmi, and Sreenivasulu G. “Area and Speed Efficient FPGA Design of S-Box AES-256 Galois Field Approch Based on Logic”. ITEGAM-JETIA 10, no. 48 (August 28, 2024): 105-114. Accessed November 23, 2024. https://itegam-jetia.org/journal/index.php/jetia/article/view/915.