Area and Speed Efficient FPGA Design of S-Box AES-256 Galois Field Approch Based on Logic. ITEGAM-JETIA, [S. l.], v. 10, n. 48, p. 105–114, 2024. DOI: 10.5935/jetia.v10i48.915. Disponível em: https://itegam-jetia.org/journal/index.php/jetia/article/view/915. Acesso em: 23 oct. 2026.