Design and Verification of an optimized 32-bit pipelined multiplier for high performance computing. ITEGAM-JETIA, [S. l.], v. 12, n. 60, p. 312–318, 2026. DOI: 10.5935/jetia.v12i60.3784. Disponível em: https://itegam-jetia.org/journal/index.php/jetia/article/view/3784. Acesso em: 22 oct. 2026.