A Novel Technique to Design Adder and Multiplier Circuits Using GNRFETs in Ternary Logic. ITEGAM-JETIA, [S. l.], v. 12, n. 60, p. 549–557, 2026. DOI: 10.5935/jetia.v12i60.3893. Disponível em: https://itegam-jetia.org/journal/index.php/jetia/article/view/3893. Acesso em: 22 oct. 2026.