Glitch-Free Clock Distribution Using Flip-Flop–Controlled Clock Gating in a 32-Bit RISC-V Architecture. ITEGAM-JETIA, [S. l.], v. 12, n. 59, p. 2130–2135, 2026. DOI: 10.5935/jetia.v12i59.3833. Disponível em: https://itegam-jetia.org/journal/index.php/jetia/article/view/3833. Acesso em: 22 oct. 2026.