«A Novel Technique to Design Adder and Multiplier Circuits Using GNRFETs in Ternary Logic». ITEGAM-JETIA 12, no. 60 (julio 31, 2026): 549–557. Accedido octubre 23, 2026. https://itegam-jetia.org/journal/index.php/jetia/article/view/3893.