Glitch-Free Clock Distribution Using Flip-Flop–Controlled Clock Gating in a 32-Bit RISC-V Architecture. JETIA [Internet]. 25 de junio de 2026 [citado 22 de octubre de 2026];12(59):2130-5. Disponible en: https://itegam-jetia.org/journal/index.php/jetia/article/view/3833