Synergistic Hybrid GDI–CNTFET Architecture for Low-Power and Area-Optimized Nanoscale VLSI Circuits. JETIA [Internet]. 31 de julio de 2026 [citado 22 de octubre de 2026];12(60):344-55. Disponible en: https://itegam-jetia.org/journal/index.php/jetia/article/view/3834