Glitch-Free Clock Distribution Using Flip-Flop–Controlled Clock Gating in a 32-Bit RISC-V Architecture

Abstract

Clock distribution contributes significantly to the dynamic power consumption of contemporary embedded processors, especially in low-power 32-bit RISC-V cores. The continuous toggling of the clock signal during idle and stall cycles not only contributes to higher switching power consumption but also poses the risk of potential clock glitches, which can impact timing correctness. In this paper, a glitch-free clock distribution scheme using flip-flop-controlled clock gating is presented for a 32-bit RISC-V processor. Unlike existing approaches based on latch-controlled clock gating, the proposed scheme uses an edge-triggered flip-flop to synchronize the clock gating signal, thus making gating decisions in a timing-safe manner only at the clock edges. The gating logic is selectively applied to the address generation unit, register file, and pipeline stages to avoid unnecessary switching activity. The proposed architecture is described in Verilog HDL and implemented using standard CMOS technology. Experimental evaluation shows a dynamic clock power reduction of approximately 30-35% with less than 2% area overhead and without degrading the critical path delay (4.765 ns total delay with positive slack). The proposed approach strikes an optimal balance between power savings, timing correctness, and ease of implementation, making it highly attractive for low-power embedded RISC-V platforms.