Design and Verification of a Fault-Tolerant AHB-to-APB Bridge with Integrated Single Error Correction (SEC) using Hamming Code.

Resumo

In modern System-on-Chip (SoC) architectures, the Advanced Micro-controller Bus Architecture (AMBA) serves as the backbone for communication between high-performance processors and low-power peripherals. The AHB-to-APB bridge is a critical interface that translates high-speed Advanced High-performance Bus (AHB) transactions into low-bandwidth Advanced Peripheral Bus (APB) signals. However, as semiconductor technology scales into the deep sub-micron regime, on-chip communication becomes increasingly susceptible to soft errors and bit-flips caused by crosstalk and electromagnetic interference. This paper proposes a fault-tolerant bridge design that integrates Single Error Correction (SEC) using Hamming Code logic. The design utilizes an 8-state Finite State Machine (FSM) to manage protocol translation and data integrity. Experimental results obtained using the Cadence Genus Synthesis tool (90nm technology) demonstrate a total area of 3464.331 um² and a total power consumption of 3.8247 mW. Functional verification confirms 100% recovery from single-bit soft errors, ensuring robust data integrity for safety-critical VLSI systems.