Synergistic Hybrid GDI–CNTFET Architecture for Low-Power and Area-Optimized Nanoscale VLSI Circuits

Resumo

As CMOS technology continues to expand to a deep sub-micron scale, standard designs are confronted with many challenges in terms of energy dissipation, leakage currents and area. Although GDI logic minimizes the number of transistors and CNTFET offers improved transport performance, it is on its own that it provides optimal performance. This paper proposes a hybrid design methodology for GDI and CNTFETs combining the structural compactness of GDI with the near ballistic electrical characteristics of 32 nm CNTFETs. The complete digital building block library, including basic logic gates, arithmetic units (half-adder, full-adder), data-routing circuits (multiplexer, encoder, decoder) and sequencing elements (D and Jk flip-flops) have been developed in the Cadence tool based on the Stanford 32nm CNTFET model. Transient, DC and AC analysis confirm full swing logic and high frequency response. The simulation results indicate that the proposed hybrid architecture achieves a reduction of 40-70 percent in power and 25-55 percent in silicon area compared to conventional CMOS and standalone GDI, CNTFET reference products, and is a much improved Power-Delay Product. These findings, together with the significantly improved PDP, make the GDI-CNTFET hybrid framework a viable and scalable solution for energy-efficient nano-electronic systems.