A Novel Technique to Design Adder and Multiplier Circuits Using GNRFETs in Ternary Logic

Resumo

The ternary logic systems provide various advantages such as faster logic and arithmetic operations, low interconnect complexity and smaller area over the traditional binary logic. This work presents the ternary logic circuit designs. A new design method is demonstrated to develop the ternary designs utilizing graphene nanoribbon field effect transistors (GNRFETs). The threshold voltage and width of GNRFET is controlled by GNR dimer line. The complex circuit designs such as half adder and multiplier circuits are proposed with reduced transistor count. The adder and multiplier schematics are designed using various ternary unary operators. The Synopsys HSPICE tool is utilized to design and simulate proposed circuits. The various performances like delay, power dissipation and PDP of proposed designs are analyzed and compared to traditional CNTFET. The proposed schematics improved the overall performance up to 42.12% than CNTFET designs. Moreover, the PDP of the proposed designs are compared to the existing literatures. The PDP is improved for the proposed circuits up to 69.64% over the existing works. Furthermore, the PVT variations impact on the proposed adder and multiplier designs are investigated. It is observed that adder and multiplier circuits showed minimum variations on the performance for the PVT variations.