Impact of Grain Boundaries on The Electrical Characteristics and Breakdown Behavior of Polycrystalline Silicon Pin Diodes: A Simulation Study

Abstract

In this paper, we present a comprehensive two-dimensional simulation program designed to model the intricate electrical characteristics of reverse-biased lateral polysilicon PIN diodes. Our methodology involves the numerical resolution of a system of partial differential equations, specifically Poisson's equation and the continuity equations for both electrons and holes, incorporating the significant effects of impact ionization. By employing this simulation approach, we are able to accurately derive the current-voltage (I-V) characteristics of the reverse-biased structure, including detailed analyses of breakdown phenomena.

The geometrical model employed in our study assumes that the polysilicon layer is composed of a sequence of crystallites with well-defined mean grain sizes. These crystallites are separated by lateral grain boundaries that run parallel to the metallurgical junction, influencing the overall electrical behavior of the diode. Our simulation results provide critical insights into the impact of these grain boundaries on the diode's performance, highlighting the role of trapping centers and their effect on the electric field distribution and carrier dynamics within the device.

Furthermore, this study discusses the implications of our findings for the design and optimization of polysilicon-based electronic components, suggesting potential improvements in device fabrication and performance. The comprehensive analysis presented in this paper not only enhances the understanding of polysilicon PIN diodes but also contributes to the broader field of semiconductor device engineering.